1. Field of the Invention
The present invention relates to a complete type an integrator designed so as to have controllable time constant and wide input and output dynamic ranges and so as to be free from occurrence of offset.
2. Description of the Prior Art
Referring to FIG. 4 of the accompanying drawings, a circuit diagram of a conventional integrator is shown, the constant of which can be controlled. In FIG. 4, diodes D10 and D11 are connected to the collectors of transistors Q20 and Q21 which constitute a differential transistor pair of a differential amplifier, respectively. Variable current sources S10 and S11 are connected to the emitters of the transistors Q20 and Q21 respectively, and a resistor R10, which defines the time constant of the integrator, is further connected between the emitters of these transistors.
A current-mirror circuit formed by transistors Q24 and Q25 and serving as an active load is connected to the collectors of transistors Q22 and Q23 which constitute a differential transistor pair of another differential amplifier, and a variable current source S12 is coupled to the connected emitters of the transistors Q22 and Q23. Output terminal 11 of the integrator is tied to the collector of the transistor Q23, and a capacitor C10 is connected between the output terminal 11 and the ground. As will be appreciated, a complete type integrator is formed by the capacitor C10 and the differential amplifier to which the capacitor C10 is connected. The time constant of the integrator can be controlled by changing current values of the variable current sources S10, S11 and S12.
Reference numeral 12 indicates a ground terminal; 8 a voltage source providing a bias voltage VBA; 9 an input signal; and 10 a power supply terminal to which power supply voltage VCC is applied.
With such an integrator, input signal 9 superimposed upon the bias voltage VBA is applied to the base of the transistor Q20, and the bias voltage VBA is imparted to the base of the transistor Q21; thus, the input signal 9 is transformed to a current depending on the resistor R10, and outputted at the collectors of the transistors Q20 and Q21.
The thus obtained current results in a voltage drop at the diodes D10 and D11, so that a current corresponding to the voltage drop is caused to flow through the capacitor C10. In this way, integrator output is derived from the output terminal 11.
With the above-described integrator, the input signal 9 is applied directly to the base of the transistor Q20 constituting the differential pair; thus, it is necessary that the bias voltage VBA be higher than the base-emitter voltage of the transistor Q20. Further, to achieve wide input and output dynamic ranges for the input signal 9, it is also necessary that the bias voltage VBA be high as to correspond to the amplitude of the input signal 9.
Thus, with the above-described conventional circuit arrangement, the power supply voltage VCC for operating the differential amplifier circuit should be high. Disadvantageously, therefore, it cannot be operated with low power supply voltage VCC.
In the case where each of the variable current sources S10, S11 and S12 is constituted by a current-mirror circuit comprising two transistors, it is required that tile power supply voltage for this integrator be as high as at least 1.5 V.
This voltage value is a sum of tile forward voltage VF (0.7 V) of the diode D11, the base-emitter voltage VBE (0.7 V) of the transistor Q23, and tile collector-emitter saturation voltage VCES (0.1 V) of tile load-side transistor constituting the variable current source S12.
Another problem is such that at the output terminal 11, an offset current is likely to appear which results from the base current of the transistors Q24 and Q25 which serve an active load circuit.